1. Technical Field
The present invention relates to a memory card controller for controlling data transfer between a host apparatus and a memory card.
2. Related Art
According to price reduction and speed-up of flash memories, video data are being recorded in a memory card not only in a field of consumer devices but also in a field of video devices for professional use.
Video data recorded in a memory card is uploaded from the memory card to a server in order to edit and archive the data. Video data to be used for professional uses have large capacity. For this reason, a reading speed of data from the memory card is requested to be, for example, a several times as high as a writing speed.
In a memory card using a flash memory or the like of which number of rewriting times is limited, in order to average the number of rewriting times, a correspondence between logical addresses and physical addresses of a nonvolatile memory in the memory card is dynamically controlled. For this reason, a logical-physical conversion table described with a correspondence between the logical addresses and the physical addresses is recorded in the nonvolatile memory. In such a configuration, a reading operation of the memory card includes two steps composed of a process for reading a physical address corresponding to a logical address specified by referring to the logical-physical conversion table, and a process for reading actual data based on the read physical address.
A reading size (transfer size) of a read command issued by a host device such as a general-purpose PC to a memory card is comparatively small. For this reason, an overhead relating to the command and an overhead relating to the logical-physical conversion table cannot be ignored.
In Japanese Patent No. 4323476, when an amount of read data reaches a data amount specified by a read command, a memory card controller pauses the reading operation. When a head address specified by a following read command is continuous with a transfer end address specified by a preceding command, the reading operation is restarted. Stopping and restarting of the reading operation are controlled by stopping and supply of a clock.
As a result, when a command for requesting data transfer to continuous regions is issued sequentially from the host apparatus, a transfer start command does not have to be issued every time when the command is received. For this reason, data transfer at a higher speed is realized.
In recent years, according to speed-up of an interface of a flash memory, a high-speed serial interface is being adopted as an external interface of a memory card. For example, a high-speed interface UHS-II of which transfer speed is 3 Gbps is standardized for SD cards.
In such a high-speed interface standard, clocks and data are not separately transferred unlike conventional memory cards, and clocks are reproduced from transferred data to be used (an embedded clock system).
Therefore, to such a high-speed interface standard, the method for stopping clocks for pausing the transfer to control the data transfer like the conventional technique disclosed in Japanese Patent No. 4323476 cannot be applied.
It is an object of the present invention to provide a memory card controller, a memory card adaptor and a memory card drive that can improve a transfer speed at the time of reading of data even when instruction of reading from a host apparatus is executed by a read command with short data length in a memory card adopting an embedded clock system.